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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. ina821 sbos893a ? august 2018 ? revised december 2018 ina821 35- v offset, 7-nv/ hz noise, low-power, precision instrumentation amplifier 1 1 features 1 ? low offset voltage: 10 v (typical), 35 v (maximum) ? gain drift: 5 ppm/ c (g = 1), 35 ppm/ c (g > 1) (maximum) ? noise: 7 nv/ hz ? bandwidth: 4.7 mhz (g = 1), 290 khz (g = 100) ? stable with 1-nf capacitive loads ? inputs protected up to 40 v ? common-mode rejection: 112 db, g = 10 (minimum) ? power supply rejection: 114 db, g = 1 (minimum) ? supply current: 650 a (maximum) ? supply range: ? single-supply: 4.5 v to 36 v ? dual-supply: 2.25 v to 18 v ? specified temperature range: ? 40 c to +125 c ? package: 8-pin soic 2 applications ? industrial process controls ? circuit breakers ? battery testers ? ecg amplifiers ? power automation ? medical instrumentation ? portable instrumentation 3 description the ina821 is a high-precision instrumentation amplifier that offers low power consumption and operates over a wide single- or dual-supply range. a single external resistor sets any gain from 1 to 10,000. the device has high precision as a result of super-beta input transistors, which provide low input offset voltage, offset voltage drift, input bias current, and input voltage and current noise. additional circuitry protects the inputs against overvoltage up to 40 v. the ina821 is optimized to provide a high common- mode rejection ratio. at g = 1, the common-mode rejection ratio exceeds 92 db across the full input common-mode range. the device is designed for low- voltage operation from a 4.5-v single supply and dual supplies up to 18 v. the ina821 is available in an 8-pin soic package and specified over the ? 40 c to +125 c temperature range. device information (1) part number package body size (nom) ina821 soic (8) 4.90 mm 3.91 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. ina821 simplified internal schematic typical distribution of input stage offset voltage drift + + + 10 k 24.7 k 10 k 10 k 10 k 24.7 k over- voltage protection over- voltage protection rg ref +vs out -vs -in +in rg o in in ref v g v v v : g 49.4 k g 1 r r g input stage offset voltage drift ( p v/ q c) amplifiers (%) 0 5% 10% 15% 20% 25% 30% -0.4 0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 tools & software technical documents ordernow productfolder support &community
2 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 device comparison table ..................................... 3 6 pin configuration and functions ......................... 4 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings ............................................................ 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 5 7.5 electrical characteristics ........................................... 6 7.6 typical characteristics - table of graphs ................. 8 7.7 typical characteristics ............................................ 10 8 detailed description ............................................ 19 8.1 overview ................................................................. 19 8.2 functional block diagram ....................................... 19 8.3 feature description ................................................. 20 8.4 device functional modes ........................................ 27 9 application and implementation ........................ 28 9.1 application information ............................................ 28 9.2 typical application .................................................. 31 9.3 other application examples .................................... 33 10 power supply recommendations ..................... 34 11 layout ................................................................... 34 11.1 layout guidelines ................................................. 34 11.2 layout example .................................................... 35 12 device and documentation support ................. 36 12.1 documentation support ........................................ 36 12.2 receiving notification of documentation updates 36 12.3 community resources .......................................... 36 12.4 trademarks ........................................................... 36 12.5 electrostatic discharge caution ............................ 36 12.6 glossary ................................................................ 36 13 mechanical, packaging, and orderable information ........................................................... 36 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (august 2018) to revision a page ? first release of production-data data sheet ........................................................................................................................... 1
3 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 device comparison table device description gain equation rg pins at pin ina821 35- v offset, 0.4 v/ c v os drift, 7-nv/ hz noise, high-bandwidth, precision instrumentation amplifier g = 1 + 49.4kohms / rg 2, 3 ina819 35- v offset, 0.4 v/ c v os drift, 8-nv/ hz noise, low-power, precision instrumentation amplifier g = 1 + 50kohms / rg 2, 3 ina828 50- v offset, 0.5 v/ c v os drift, 7-nv/ hz noise, low-power, precision instrumentation amplifier g = 1 + 50kohms / rg 1, 8 ina333 25- v v os , 0.1 v/ c v os drift, 1.8-v to 5-v, rro, 50- a i q , chopper-stabilized ina g = 1 + 100kohms / rg 1, 8 pga280 20-mv to 10-v programmable gain ia with 3-v or 5-v differential output; analog supply up to 18 v digital programmable n/a ina159 g = 0.2 v differential amplifier for 10-v to 3-v and 5-v conversion g = 0.2 v/v n/a pga112 precision programmable gain op amp with spi digital programmable n/a
4 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 6 pin configuration and functions d package 8-pin soic top view pin functions pin i/o description name no. ? in 1 i negative (inverting) input +in 4 i positive (noninverting) input out 7 o output rg 2, 3 ? gain setting pin. place a gain resistor between pin 2 and pin 3. ref 6 i reference input. this pin must be driven by a low impedance source. ? vs 5 ? negative supply +vs 8 ? positive supply 1 in 8 +vs 2 rg 7 out 3 rg 6 ref 4 +in 5 -vs
5 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) short-circuit to v s / 2. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage ? 20 20 v signal input pins voltage ? 40 40 v ref pin ? 20 20 signal output pins (-v s ) - 0.5 (+v s ) + 0.5 v output short-circuit (2) continuous operating temperature, t a ? 50 150 c junction temperature, t j 175 storage temperature, t stg ? 65 150 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 1500 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 750 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit supply voltage v s single-supply 4.5 36 v dual-supply 2.25 18 specified temperature specified temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) ina821 unit d (soic) 8 pins r ja junction-to-ambient thermal resistance 119.6 c/w r jc(top) junction-to-case (top) thermal resistance 66.3 c/w r jb junction-to-board thermal resistance 61.9 c/w jt junction-to-top characterization parameter 20.5 c/w jb junction-to-board characterization parameter 61.4 c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a c/w
6 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) total offset, referred-to-input (rti): v os = (v osi ) + (v oso / g). (2) offset drifts are uncorrelated. input-referred offset drift is calculated using: v os(rti) = [ v osi 2 + ( v oso / g) 2 ] (3) specified by characterization. (4) input voltage range of the ina821 input stage. the input range depends on the common-mode voltage, differential voltage, gain, and reference voltage. see typical characteristic curves figure 51 through figure 54 for more information. (5) total rti voltage noise is equal to: e n(rti) = [e ni 2 + (e no / g) 2 ] (6) the values specified for g > 1 do not include the effects of the external gain-setting resistor, " r g " . 7.5 electrical characteristics at t a = 25 c, v s = 15 v, r l = 10 k ? , v ref = 0 v, and g = 1 (unless otherwise noted) parameter test conditions min typ max unit input v osi input stage offset voltage (1) (2) g = 100, rti 10 35 v t a = ? 40 c to 125 c (3) 75 v vs temperature, t a = ? 40 c to 125 c 0.4 v/ c v oso output stage offset voltage (1) (2) g = 1 50 350 v t a = ? 40 c to 125 c (3) 850 v vs temperature, t a = ? 40 c to 125 c 5 v/ c psrr power-supply rejection ratio g = 1, rti 110 120 db g = 10, rti 114 130 g = 100, rti 130 135 g = 1000, rti 136 140 z id differential impedance 100 || 1 g || pf z ic common-mode impedance 100 || 7 g ? || pf rfi filter, ? 3-db frequency 45 mhz v cm operating input range (4) (v ? ) + 2 (v+) ? 2 v v s = 2.25 v to 18 v, t a = ? 40 c to 125 c see figure 51 to figure 54 input overvoltage range t a = ? 40 c to 125 c (3) 40 v cmrr common-mode rejection ratio at dc to 60 hz, rti, v cm = (v ? ) + 2 v to (v+) ? 2 v, g = 1 92 105 db at dc to 60 hz, rti, v cm = (v ? ) + 2 v to (v+) ? 2 v, g = 10 112 125 at dc to 60 hz, rti, v cm = (v ? ) + 2 v to (v+) ? 2 v, g = 100 132 145 at dc to 60 hz, rti, v cm = (v ? ) + 2 v to (v+) ? 2 v, g = 1000 140 150 bias current i b input bias current v cm = v s / 2 0.15 0.5 na t a = ? 40 c to 125 c 2 i os input offset current v cm = v s / 2 0.15 0.5 na t a = ? 40 c to 125 c 2 noise voltage e ni input stage voltage noise (5) f = 1 khz, g = 100, r s = 0 ? 7 nv/ hz f b = 0.1 hz to 10 hz, g = 100, r s = 0 ? 0.14 v pp e no output stage voltage noise (5) f = 1 khz, r s = 0 ? 65 nv/ hz f b = 0.1 hz to 10 hz, r s = 0 ? 2.5 v pp i n noise current f = 1 khz 130 fa/ hz f b = 0.1 hz to 10 hz, g = 100 4.7 pa pp gain g gain equation 1 + (49.4 k ? / r g ) v/v range of gain 1 1000 v/v ge gain error g = 1, v o = 10 v 0.005% 0.025% g = 10, v o = 10 v 0.025% 0.15% g = 100, v o = 10 v 0.025% 0.15% g = 1000, v o = 10 v 0.05% gain vs temperature (6) g = 1, t a = ? 40 c to 125 c 5 ppm/ c g > 1, t a = ? 40 c to 125 c 35
7 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k ? , v ref = 0 v, and g = 1 (unless otherwise noted) parameter test conditions min typ max unit gain nonlinearity g = 1 to 10, v o = ? 10 v to 10 v, r l = 10 k ? 1 10 ppm g = 100, v o = ? 10 v to 10 v, r l = 10 k ? 15 g = 1000, v o = ? 10 v to 10 v, r l = 10 k ? 10 g = 1 to 100, v o = ? 10 v to 10 v, r l = 2 k ? 30 output voltage swing (v ? ) + 0.15 (v+) ? 0.15 v load capacitance stability 1000 pf z o closed-loop output impedance f = 10 khz 1.3 ? i sc short-circuit current continuous to v s / 2 20 ma frequency response bw bandwidth, ? 3 db g = 1 4.7 mhz g = 10 970 khz g = 100 290 g = 1000 30 sr slew rate g = 1, v o = 10 v 2.0 v/ s t s settling time 0.01%, g = 1 to 100, v step = 10 v 6 s 0.01%, g = 1000, v step = 10 v 40 0.001%, g = 1 to 100, v step = 10 v 10 0.001%, g = 1000, v step = 10 v 50 reference input r in input impedance 10 k ? voltage range (v ? ) (v+) v gain to output 1 v/v reference gain error 0.01% power supply v s power-supply voltage single-supply 4.5 36 v dual-supply 2.25 18 i q quiescent current v in = 0 v 600 650 a vs temperature, t a = ? 40 c to 125 c 870
8 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6 typical characteristics - table of graphs at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) table 1. table of graphs description figure typical distribution of input stage offset voltage figure 1 typical distribution of input stage offset voltage drift figure 2 typical distribution of output stage offset voltage figure 3 typical distribution of output stage offset voltage drift figure 4 input stage offset voltage vs temperature figure 5 output stage offset voltage vs temperature figure 6 typical distribution of input bias current t a = 25 c figure 7 typical distribution of input bias current t a = 90 c figure 8 typical distribution of input offset current figure 9 input bias current vs temperature figure 10 input offset current vs temperature figure 11 typical cmrr distribution g=1 figure 12 typical cmrr distribution g=10 figure 13 . cmrr vs temperature g=1 figure 14 cmrr vs temperature g=10 figure 15 input current vs input overvoltage figure 16 cmrr vs frequency (rti) figure 17 cmrr vs frequency (rti, 1-k source imbalance) figure 18 positive psrr vs frequency (rti) figure 19 negative psrr vs frequency (rti) figure 20 gain vs frequency figure 21 voltage noise spectral density vs frequency (rti) figure 22 current noise spectral density vs frequency (rti) figure 23 0.1-hz to 10-hz rti voltage noise g = 1 figure 24 0.1-hz to 10-hz rti voltage noise g = 1000 figure 25 0.1-hz to 10-hz rti current noise figure 26 typical distribution of gain error g=1 figure 27 typical distribution of gain error g=10 figure 28 input bias current vs common-mode voltage figure 29 gain error vs temperature g = 1 figure 30 gain error vs temperature g = 10 figure 31 .supply current vs temperature figure 32 gain nonlinearity g = 1 figure 33 gain nonlinearity g = 10 figure 34 offset voltage vs negative common-mode voltage figure 35 offset voltage vs positive common-mode voltage figure 36 positive output voltage swing vs output current figure 37 negative output voltage swing vs output current figure 38 short circuit current vs temperature figure 39 large-signal frequency response figure 40 thd+n vs frequency figure 41 overshoot vs capacitive loads figure 42 small-signal response g = 1 figure 43 small-signal response g = 10 figure 44 small-signal response g = 100 figure 45
9 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics - table of graphs (continued) table 1. table of graphs (continued) description figure small-signal response g = 1000 figure 46 large signal step response figure 47 closed-loop output impedance figure 48 differential-mode emi rejection ratio figure 49 common-mode emi rejection ratio figure 50 input common-mode voltage vs output voltage g = 1, v s = 5 v figure 51 input common-mode voltage vs output voltage g = 100, v s = 5 v figure 52 input common-mode voltage vs output voltage v s = 5 v figure 53 input common-mode voltage vs output voltage v s = 15 v figure 54
10 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7 typical characteristics at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) n = 2667 mean = 3.1 v std. dev. = 8.1 v figure 1. typical distribution of input stage offset voltage n = 81 mean = -0.03 v/ c std. dev. = 0.09 v/ c figure 2. typical distribution of input stage offset voltage drift n = 2667 mean = 7.7 v std. dev. = 50.7 v figure 3. typical distribution of output stage offset voltage n = 81 mean = ? 1.09 v/ c std. dev. = 0.94 v/ c figure 4. typical distribution of output stage offset voltage drift 81 units figure 5. input stage offset voltage vs temperature 81 units figure 6. output stage offset voltage vs temperature input stage offset voltage ( p v) amplifiers (%) 0 5% 10% 15% -30 30 -25 -20 -15 -10 -5 0 5 10 15 20 25 input stage offset voltage drift ( p v/ q c) amplifiers (%) 0 5% 10% 15% 20% 25% 30% -0.4 0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 output stage offset voltage ( p v) amplifiers (%) 0 5% 10% 15% 0 -200 200 -100 100 output offset voltage drift ( p v/ q c) amplifiers (%) 0 1% 2% 3% 4% 5% 6% 7% 8% 9% 10% 11% 12% 13% 14% 15% 16% 0 -5 5 -4 -3 -2 -1 1 2 3 4 temperature(c) input-referred offset voltage ( p v) -50 -25 0 25 50 75 100 125 150 -500 -400 -300 -200 -100 0 100 200 300 400 500 mean +3 v -3 v temperature(c) input-referred offset voltage ( p v) -50 -25 0 25 50 75 100 125 150 -100 -75 -50 -25 0 25 50 75 100 mean +3 v -3 v
11 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) n = 292 mean = 45 pa std. dev. = 62 pa t a = 25 c figure 7. typical distribution of input bias current t a = 25 c n = 292 mean = 34 pa std. dev. = 52 pa t a = 90 c figure 8. typical distribution of input bias current t a = 90 c n = 292 mean = 34 pa std. dev. = 52 pa t a = 25 c figure 9. typical distribution of input offset current n = 294 g=1 figure 10. input bias current vs temperature n = 294 g=1 figure 11. input offset current vs temperature n = 294 mean = 4.87 v/v std. dev. = 4.14 v/v g=1 figure 12. typical cmrr distribution g=1 common-mode rejection ratio ( p v/v) amplifiers (%) 0 5% 10% 15% 20% 25% 0 -20 20 -16 -12 -8 -4 4 8 12 16 temperature ( q c) input bias current (na) -50 -30 -10 10 30 50 70 90 110 130 150 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 avg 3 v 3 v temperature ( q c) input offset current (na) -50 -30 -10 10 30 50 70 90 110 130 150 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 avg 3sig 3sig input bias current (pa) amplifiers (%) 0 5% 10% 15% 20% 0 -300 300 -200 -100 100 200 input bias current (pa) amplifiers (%) 0 5% 10% 15% 20% 0 -200 200 -150 -100 -50 50 100 150
12 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) n = 294 mean = 0.51 v/v std. dev. = 0.42 v/v g=10 figure 13. typical cmrr distribution g=10 n = 5 g = 1 figure 14. cmrr vs temperature g = 1 n = 5 g = 10 figure 15. cmrr vs temperature g = 10 v s = 18 v figure 16. input current vs input overvoltage figure 17. cmrr vs frequency (rti) figure 18. cmrr vs frequency (rti, 1-k source imbalance) common-mode rejection ratio ( p v/v) amplifiers (%) 0 5% 10% 15% 20% 25% 30% 0 -2 2 -1.5 -1 -0.5 0.5 1 1.5 temperature ( q c) common-mode rejection ratio (db) -50 -25 0 25 50 75 100 125 150 75 100 125 150 175 unit 1 unit 2 unit 3 unit 4 unit 5 input voltage (v) input current (ma) output voltage (v) -50 -40 -30 -20 -10 0 10 20 30 40 50 -10 -20 -8 -16 -6 -12 -4 -8 -2 -4 0 0 2 4 4 8 6 12 8 16 10 20 input current output voltage frequency (hz) cmrr (db) 0 20 40 60 80 100 120 140 10 100 1k 10k 100k 1m g = 1 g = 10 g = 100 g = 1000 frequency (hz) cmrr (db) 0 20 40 60 80 100 120 140 160 10 100 1k 10k 100k 1m 10m g= 1 g= 10 g= 100 g= 1000 temperature ( q c) common-mode rejection ratio (db) -50 -25 0 25 50 75 100 125 150 50 75 100 125 150 unit 1 unit 2 unit 3 unit 4 unit 5
13 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) figure 19. positive psrr vs frequency (rti) figure 20. negative psrr vs frequency (rti) figure 21. gain vs frequency figure 22. voltage noise spectral density vs frequency (rti) figure 23. current noise spectral density vs frequency (rti) g = 1 figure 24. 0.1-hz to 10-hz rti voltage noise g = 1 frequency (hz) gain (db) -60 -40 -20 0 20 40 60 80 100 1k 10k 100k 1m 10m g = 1 g = 10 g = 100 g = 1000 freq voltage noise spectral density (nv/ ? hz) 100m 1 10 100 1k 10k 100k 10 100 1000 g = 1 g = 10 g = 100 g = 1000 frequency (hz) positive power supply rejection ration (db) -40 -20 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k g = 1 g = 10 g = 100 g = 1000 frequency (hz) negative power supply rejection ratio (db) -40 -20 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k g = 1 g = 10 g = 100 g = 1000 frequency (hz) current noise spectral density (fa/ ? hz) 100m 1 10 100 1k 10k 10 100 1k time (1 s/div) noise (0.5 p v/div)
14 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) g = 1000 figure 25. 0.1-hz to 10-hz rti voltage noise g = 1000 g = 1 figure 26. 0.1-hz to 10-hz rti current noise n = 294 mean = 35 ppm std. dev. = 133 ppm g=1 figure 27. typical distribution of gain error g=1 n = 293 mean = 152 ppm std. dev. = 291 ppm g=10 figure 28. typical distribution of gain error g=10 v s = 15 v figure 29. input bias current vs common-mode voltage average of 294 units g = 1 figure 30. gain error vs temperature g = 1 common mode voltage (v) input bias current (na) -15 -12 -9 -6 -3 0 3 6 9 12 15 -0.5 -0.3 -0.1 0.1 0.3 0.5 45 q c 25 q c 125 q c temperature ( q c) gain error (ppm) -50 -25 0 25 50 75 100 125 150 -40 -20 0 20 40 60 80 100 time (1 s/div) noise (0.5 pa/div) time (1 s/div) noise (20 nv/div) gain error (ppm) amplifiers (%) 0 2% 4% 6% 8% 10% 12% 14% 16% 18% 20% 0 -900 900 -600 -300 300 600 gain error (ppm) amplifiers (%) 0 2.5% 5% 7.5% 10% 12.5% 15% 0 -250 250 -200 -150 -100 -50 50 100 150 200
15 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) average of 294 units g = 10 figure 31. gain error vs temperature g = 10 figure 32. supply current vs temperature g = 1 figure 33. gain nonlinearity g = 1 g = 10 figure 34. gain nonlinearity figure 35. offset voltage vs negative common-mode voltage figure 36. offset voltage vs positive common-mode voltage input common-mode voltage (v) offset voltage ( p v) 12 12.4 12.8 13.2 13.6 14 14.4 14.8 -50 -25 0 25 50 75 100 125 150 40 q c 25 q c 85 q c 125 q c output voltage (v) nonlinearity (ppm) -10 -8 -6 -4 -2 0 2 4 6 8 10 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 input common-mode voltage (v) offset voltage ( p v) -15 -14.6 -14.2 -13.8 -13.4 -13 -12.6 -12.2 -75 -50 -25 0 25 50 75 100 125 150 175 40 q c 25 q c 85 q c 125 q c temperature ( q c) i q (ma) -50 -30 -10 10 30 50 70 90 110 130 150 0.3 0.36 0.42 0.48 0.54 0.6 0.66 0.72 0.78 0.84 0.9 vs = r 15 v vs = r 2.25 v output voltage (v) nonlinearity (ppm) -10 -8 -6 -4 -2 0 2 4 6 8 10 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 temperature ( q c) gain error (ppm) -50 -25 0 25 50 75 100 125 150 -1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500
16 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) figure 37. positive output voltage swing vs output current figure 38. negative output voltage swing vs output current figure 39. short circuit current vs temperature figure 40. large-signal frequency response 500-khz measurement bandwidth 1-v rms output voltage 100-k load figure 41. thd+n vs frequency figure 42. overshoot vs capacitive loads output current (ma) output voltage (v) 0 2 4 6 8 10 12 14 16 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 15 -40 q c 25 q c 85 q c 125 q c output current (ma) output voltage (v) 0 2 4 6 8 10 12 14 16 -15 -14.9 -14.8 -14.7 -14.6 -14.5 -14.4 -14.3 -14.2 -14.1 -14 -40 q c 25 q c 85 q c 125 q c capacitive load (pf) overshoot (%) 0 5 10 15 20 25 30 35 40 45 50 1 10 100 1000 positive overshoot negative overshoot temperature ( q c) short-circuit current (ma) -50 -30 -10 10 30 50 70 90 110 130 150 -60 -50 -40 -30 -20 -10 0 10 20 30 40 i sc, source i sc, sink frequency (hz) total harmonic distortion + noise (%) -40 10 100 1k 10k 100k 0.001 0.01 0.1 1 -60-80 -100 total harmonic distortion + noise (db) g = 1 g = 10 g = 100 0 2 4 6 8 10 12 14 16 18 20 100 1k 10k 100k 1m 10m v s = r 15 v v s = r 5 v
17 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) g = 1 r l = 10 k c l = 100 pf figure 43. small-signal response g = 10 r l = 10 k c l = 100 pf figure 44. small-signal response g = 100 r l = 10 k c l = 100 pf figure 45. small-signal response g = 1000 r l = 10 k c l = 100 pf figure 46. small-signal response figure 47. large signal step response figure 48. closed-loop output impedance time (s) output amplidute (mv) -5 -2.5 0 2.5 5 7.5 10 12.5 15 -75 -50 -25 0 25 50 75 time (s) output amplidute (mv) -25 0 25 50 75 -75 -50 -25 0 25 50 75 time (s) output amplidute (mv) -5 -2.5 0 2.5 5 7.5 10 12.5 15 -75 -50 -25 0 25 50 75 time (s) output amplidute (mv) -5 -2.5 0 2.5 5 7.5 10 12.5 15 -75 -50 -25 0 25 50 75 frequency (hz) output impedence ( : ) 1 10 100 1k 10k 100k 1m 10m 0.1 1 10 100 time (10 s/div) amplitude (2 v/div) output input
18 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) at t a = 25 c, v s = 15 v, r l = 10 k , v ref = 0 v, and g = 1 (unless otherwise noted) figure 49. differential-mode emi rejection ratio figure 50. common-mode emi rejection ratio v s = 5 v g = 1 figure 51. input common-mode voltage vs output voltage v s = 5 v g = 100 figure 52. input common-mode voltage vs output voltage v s = 5 v v ref = 0 v figure 53. input common-mode voltage vs output voltage v s = 15 v v ref = 0 v figure 54. input common-mode voltage vs output voltage frequency (hz) emirr (db) 0 20 40 60 80 100 120 140 10m 100m 1g 10g 0 1 2 3 4 5 0 1 2 3 4 5 6 common-mode voltage (v) output voltage (v) vref = 0 v vref = 2.5 v c006 frequency (hz) emirr (db) 0 20 40 60 80 100 120 10m 100m 1g 10g 0 1 2 3 4 5 0 1 2 3 4 5 6 common-mode voltage (v) output voltage (v) vref = 0 v vref = 2.5 v c006 -20 -15 -10 -5 0 5 10 15 20 10 0 10 20 common-mode voltage (v) output voltage (v) g = 1 g = 100 c006 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 4 2 0 2 4 6 common-mode voltage (v) output voltage (v) g = 1 g = 100 c006
19 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the ina821 is a monolithic precision instrumentation amplifier incorporating a current-feedback input stage and a 4-resistor difference amplifier output stage. the differential input voltage is buffered by q 1 and q 2 and is forced across r g , which causes a signal current to flow through r g , r 1 , and r 2 . the output difference amplifier (a 3 ) removes the common-mode component of the input signal and refers the output signal to the ref pin. the v be and voltage drop across r 1 and r 2 produces output voltages on a 1 and a 2 that are approximately 0.8 v lower than the input voltages. each input is protected by two field-effect transistors (fets) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. when excessive voltage is applied, these transistors limit input current to approximately 8 ma. 8.2 functional block diagram + r 1 24.7 k r b v b +v s -v s +v s -v s +v s -v s +v s -v s + + +v s -v s super- npn super- npn r g (external) +v s -v s over-voltage protection over-voltage protection r b -in +in ref out q 1 q 2 a 1 a 2 a 3 +v s i b cancellation i b cancellation r 2 24.7 k 10 k 10 k 10 k 10 k copyright ? 2017, texas instruments incorporated rg rg
20 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3 feature description 8.3.1 setting the gain figure 55 shows that the gain of the ina821 is set by a single external resistor (r g ) connected between the rg pins (pins 1 and 8). figure 55. simplified diagram of the ina821 with gain and output equations the value of r g is selected according to: (1) table 2 lists several commonly used gains and resistor values. the 49.4-k ? term in equation 1 is a result of the sum of the two internal 24.7-k feedback resistors. these on-chip resistors are laser-trimmed to accurate absolute values. the accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the ina821. as shown in figure 55 and explained in more details in section layout , it is highly recommended to connect low-esr, 0.1- f ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. table 2. commonly-used gains and resistor values desired gain r g ( ) nearest 1% r g ( ) 1 nc nc 2 49.4 k 49.9 k 5 12.35 k 12.4 k 10 5.489 k 5.49 k 20 2.600 k 2.61 k 50 1.008 k 1 k 100 499 499 200 248 249 500 99 100 1000 49.4 49.9 : g 49.4 k g 1 r + + + 10 k 24.7 k 10 k 10 k 10 k 24.7 k overvoltage protection overvoltage protection rg ref +vs v- out v+ -vs -in +in : g 49.4 k g 1 r o in in ref v g v v v copyright ? 2017, texas instruments incorporated rg r g
21 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.1.1 gain drift the stability and temperature drift of the external gain setting resistor (r g ) affects gain. the contribution of r g to gain accuracy and drift is determined from equation 1 . the best gain drift of 5 ppm/ (maximum) is achieved when the ina821 uses g = 1 without r g connected. in this case, gain drift is limited by the slight mismatch of the temperature coefficient of the integrated 10-k resistors in the differential amplifier (a 3 ). at gains greater than 1, gain drift increases as a result of the individual drift of the 24.7-k resistors in the feedback of a 1 and a 2 relative to the drift of the external gain resistor (r g .) the low temperature coefficient of the internal feedback resistors significantly improves the overall temperature stability of applications using gains greater than 1 v/v over alternate options. low resistor values required for high gain make wiring resistance important. sockets add to the wiring resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately 100 or greater. to ensure stability, avoid parasitic capacitance of more than a few picofarads at r g connections. careful matching of any parasitics on the r g pins maintains optimal cmrr over frequency; see figure 17 .
22 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.2 emi rejection texas instruments developed a method to accurately measure the immunity of an amplifier over a broad frequency spectrum extending from 10 mhz to 6 ghz. this method uses an emi rejection ratio (emirr) to quantify the ability of the ina821 to reject emi. the offset resulting from an input emi signal is calculated using equation 2 : where ? v rf_peak is the peak amplitude of the input emi signal. (2) figure 56 and figure 57 show the ina821 emirr graph for differential and common-mode emi rejection across this frequency range. table 3 shows the emirr values for the ina821 at frequencies encountered in real-world applications. applications listed in table 3 are centered on or operated near the particular frequency shown. depending on the end-system requirements, additional emi filters may be required near the signal inputs of the system, as well as incorporating known good practices such as using short traces, low-pass filters, and damping resistors combined with parallel and shielded signal routing. figure 56. common-mode emirr testing figure 57. differential mode emirr testing emirr (db) 2 rf _ peak 20 os p v v 10 100 mv ? ? 1 ? ' ? ? ? 1 frequency (hz) emirr (db) 0 20 40 60 80 100 120 140 10m 100m 1g 10g frequency (hz) emirr (db) 0 20 40 60 80 100 120 10m 100m 1g 10g
23 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated table 3. ina821 emirr for frequencies of interest frequency application or allocation differential emirr common-mode emirr 400 mhz mobile radio, mobile satellite, space operation, weather, radar, ultrahigh- frequency (uhf) applications 60 db 88 db 900 mhz global system for mobile communications (gsm) applications, radio communication, navigation, gps (up to 1.6 ghz), gsm, aeronautical mobile, uhf applications 58 db 60 db 1.8 ghz gsm applications, mobile personal communications, broadband, satellite, l-band (1 ghz to 2 ghz) 66 db 89 db 2.4 ghz 802.11b, 802.11g, 802.11n, bluetooth ? , mobile personal communications, industrial, scientific and medical (ism) radio band, amateur radio and satellite, s-band (2 ghz to 4 ghz) 73 db 98 db 3.6 ghz radiolocation, aero communication and navigation, satellite, mobile, s-band 99 db 111 db 5 ghz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, c-band (4 ghz to 8 ghz) 83 db 91 db 8.3.3 input common-mode range the linear input voltage range of the ina821 input circuitry extends within 2 v of power supplies and maintains excellent common-mode rejection throughout this range. the common-mode range for the most common operating conditions are shown in figure 58 , figure 53 and figure 54 . the common-mode range for other operating conditions is best calculated using the ina common-mode range calculating tool . the ina821 device operates over a wide range of power supplies and v ref configurations, which provides a comprehensive guide to common-mode range limits for all possible conditions. v s = 5 v g = 1 figure 58. input common-mode voltage vs output voltage v s = 5 v g = 100 figure 59. input common-mode voltage vs output voltage 0 1 2 3 4 5 0 1 2 3 4 5 6 common-mode voltage (v) output voltage (v) vref = 0 v vref = 2.5 v c006 0 1 2 3 4 5 0 1 2 3 4 5 6 common-mode voltage (v) output voltage (v) vref = 0 v vref = 2.5 v c006
24 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated v s = 5 v v ref = 0 v figure 60. input common-mode voltage vs output voltage v s = 15 v v ref = 0 v figure 61. input common-mode voltage vs output voltage 8.3.4 input protection the inputs of the ina821 device are individually protected for voltages up to 40 v. for example, a condition of ? 40 v on one input and 40 v on the other input does not cause damage. internal circuitry on each input provides low series impedance under normal signal conditions. if the input is overloaded, the protection circuitry limits the input current to a value of approximately 8 ma. figure 62. input current path during an overvoltage condition +v s -v s overvoltage protection in input transistor +v -v + input voltage source zd1 zd2 -20 -15 -10 -5 0 5 10 15 20 10 0 10 20 common-mode voltage (v) output voltage (v) g = 1 g = 100 c006 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 4 2 0 2 4 6 common-mode voltage (v) output voltage (v) g = 1 g = 100 c006
25 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated during an input overvoltage condition, current flows through the input protection diodes into the power supplies; see figure 62 . if the power supplies are unable to sink current, then zener diode clamps (zd1 and zd2 in figure 62 ) must be placed on the power supplies to provide a current pathway to ground. figure 63 shows the input current for input voltages from ? 40 v to 40 v when the ina821 is powered by 15-v supplies. figure 63. input current vs input overvoltage 8.3.5 operating voltage the ina821 operates over a power-supply range of 4.5 v to 36 v ( 2.25 v to 18 v). caution supply voltages higher than 40 v ( 20 v) can permanently damage the device. parameters that vary over supply voltage or temperature are shown in the typical characteristics section of this data sheet. input voltage (v) input current (ma) output voltage (v) -50 -40 -30 -20 -10 0 10 20 30 40 50 -10 -20 -8 -16 -6 -12 -4 -8 -2 -4 0 0 2 4 4 8 6 12 8 16 10 20 input current output voltage
26 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.6 error sources most modern signal-conditioning systems calibrate errors at room temperature. however, calibration of errors that result from a change in temperature is normally difficult and costly. therefore, minimizing these errors is important by choosing high-precision components such as the ina821 that have improved specifications in critical areas that impact the precision of the overall system. figure 64 shows an example application. figure 64. example application with g = 10 v/v and 1 v output voltage resistor-adjustable devices (such as the ina821) show the lowest gain error in g = 1 because of the inherently well-matched drift of the internal resistors of the differential amplifier. at gains greater than 1, (for instance, g = 10 v/v or g = 100 v/v) the gain error becomes a significant error source because of the contribution of the resistor drift of the 24.7-k feedback resistors in conjunction with the external gain resistor. except for very high gain applications, the gain drift is by far the largest error contributor compared to other drift errors, such as offset drift. the ina821 offers excellent gain error over temperature for both g > 1 and g = 1 (no external gain resistor). table 5 summarizes the major error sources in common ina applications and compares the three cases of g = 1 (no external resistor) and g = 10 (5.49-k external resistor) and g = 100 (499- external resistor). all calculations are assuming an output voltage of v out = 1 v. thus, the input signal v diff which is given by v diff = v out /g will exhibit smaller and smaller amplitudes with increasing gain g, e.g. v diff = 1 mv at g = 1000 in this example. all calculations refer the error to the input for easy comparison and system evaluation. as can be seen in table 5 , errors generated by the input stage (such as input offset voltage) are more dominant at higher gain while the effects of output stage are suppressed because they are divided by the gain when referring them back to the input. note that the gain error and gain drift error are much more significant for gains greater than 1 because of the contribution of the resistor drift of the 24.7-k feedback resistors in conjunction with the external gain resistor. in most applications, static errors (absolute accuracy errors) can readily be removed during calibration in production, while the drift errors will be the key factors limiting overall system performance. table 4. system specifications for error calculation quantity value vout (v) 1 vcm (v) 10 vs(v) 1 rs+ ( ) 1000 rs- ( ) 999 rg tolerance (%) 0.01 rg drift (ppm/ c) 10 temp range upper limit ( c) 105 5.49k vcm = 10 v +15v v out = 1v -15v r s+ = 1k c1 c2 rg ref +vs vs ina rg r s- = 0.99k v diff = v out / g
27 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated table 5. error calculation error source error calculation ina821 specification g = 1 error (ppm) g = 100 error (ppm) g = 1000 error (ppm) absolute accuracy at 25 c input offset voltage ( v) v osi / v diff 35 35 350 3500 output offset voltage ( v) v oso / (g v diff ) 350 350 350 350 input offset current (na) i os maximum (r s+ , r s ? ) / v diff 0.5 1 5 50 cmrr (db) (min) v cm / (10 cmrr/20 v diff ) 92 (g = 1), 112 (g = 10), 132 (g = 100) 251 251 251 psrr (db) (min) (v cc -v s )/ (10 psrr/20 v diff ) 110 (g = 1), 114 (g = 10), 130 (g = 100) 3 20 32 gain error from ina (%) (max) ge(%) 10 4 0.02 (g = 1), 0.15 (g = 10, 100) 200 1500 1500 gain error from external resistor rg (%) (max) ge(%) 10 4 0.01 100 100 100 total absolute accuracy error (ppm) at 25 c, worst case sum of all errors 940 2576 5738 total absolute accuracy error (ppm) at 25 c, average rms sum of all errors 487 1603 3834 drift to 105 c gain drift from ina (ppm/ c) (max) gtc (t a ? 25) 5 (g = 1), 35 (g = 10, 100) 400 2800 2800 gain drift from external resistor rg (ppm/ c) (max) gtc (t a ? 25) 10 800 800 800 input offset voltage drift ( v/ c) (max) (v osi_tc / v diff ) (t a ? 25) 0.4 32 320 3200 output offset voltage drift ( v/ c) [v oso_tc / ( g v diff )] (t a ? 25) 5 400 400 400 offset current drift (pa/ c) i os_tc maximum (r s+ , r s ? ) (t a ? 25) / v diff 20 2 16 160 total drift error to 105 c (ppm), worst case sum of all errors 1634 4336 7360 total drift error to 105 c (ppm), typical rms sum of all errors 980 2957 4348 resolution gain nonlinearity (ppm of fs) 10 (g = 1, 10), 15 (g = 100) 10 10 15 voltage noise (@1 khz) ( vpp) e ni = 7, e no = 65 1335 886 3566 current noise (@1khz) (pa/ hz) i n maximum (r s+ , r s ? ) sqrt (bw) / v diff 0.13 0.4 2 11 total resolution error (ppm), worst case sum of all errors 1345 896 3581 total resolution error (ppm), typical rms sum of all errors 1335 886 3566 total error total error (ppm), worst case sum of all errors 3919 7808 16724 total error (ppm), typical rms sum of all errors 1726 3478 6806 8.4 device functional modes the ina821 has a single functional mode and is operational when the power supply voltage is greater than 4.5 v ( 2.25 v). the maximum power-supply voltage for the ina821 is 36 v ( 18 v). (e + ni 2 e no 2 g 6 v diff bw
28 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information 9.1.1 reference pin the output voltage of the ina821 is developed with respect to the voltage on the reference pin (ref.) often in dual-supply operation, the reference pin (pin 6) connects to the low-impedance system ground. in single-supply operation, offsetting the output signal to a precise midsupply level is useful (for example, 2.5 v in a 5-v supply environment). to accomplish this level shift, a voltage source must be connected to the ref pin to level-shift the output so that the ina821 drives a single-supply adc. the voltage source applied to the reference pin must have a low output impedance. as shown in figure 65 , any resistance at the reference pin ( r ref in figure 65 ) is in series with one of the internal 10-k resistors. figure 65. parasitic resistance shown at the reference pin the parasitic resistance at the reference pin (r ref ) creates an imbalance in the four resistors of the internal difference amplifier, resulting in degraded common-mode rejection ratio (cmrr). figure 66 shows the degradation in cmrr of the ina821 for increasing resistance at the reference pin. for the best performance, keep the source impedance to the ref pin (r ref ) below 5 . + + + 10 k 24.7 k 10 k 10 k 10 k 24.7 k over- voltage protection over- voltage protection rg ref +vs v- out v+ -vs -in +in rg r ref r g
29 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) figure 66. the effect of increasing resistance at the reference pin voltage reference devices are an excellent option for providing a low-impedance voltage source for the reference pin. however, if a resistor voltage divider generates a reference voltage, the divider must be buffered by an op amp as shown in figure 67 to avoid cmrr degradation. figure 67. using an op amp to buffer reference voltages 9.1.2 input bias current return path the input impedance of the ina821 is extremely high (approximately 100 g .) however, a path must be provided for the input bias current of both inputs. this input bias current is typically 150 pa. high input impedance means that this input bias current changes little with varying input voltage. input circuitry must provide a path for this input bias current for proper operation. figure 68 shows various provisions for an input bias current path. without a bias current path, the inputs float to a potential that exceeds the common-mode range of the ina821 and the input amplifiers saturate. if the differential source resistance is low, the bias current return path connects to one input (as shown in the thermocouple example in figure 68 ). with a higher source impedance, using two equal resistors provides a balanced input with possible advantages of a lower input offset voltage as a result of bias current and better high-frequency common-mode rejection. 0 20 40 60 80 100 120 10 100 1k 10k common-mode rejection ratio frequency (hz) c001 +in in rg ref +vs vs ina821 5 v + opa191 100 k 5 v 1 f 5 v 100 k out copyright ? 2017, texas instruments incorporated rg r g
30 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated application information (continued) (1) center tap provides bias current return. figure 68. providing an input common-mode current path ti device 47 k w 47 k w ti device 10 k w microphone, hydrophone, and so forth thermocouple ti device center tap provides bias current return. copyright ? 2017, texas instruments incorporated
31 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2 typical application figure 69 shows a three-pin programmable-logic controller (plc) design for the ina821. this plc reference design accepts inputs of 10 v or 20 ma. the output is a single-ended voltage of 2.5 v 2.3 v (or 200 mv to 4.8 v). typically, plcs have these input and output ranges. figure 69. plc input ( 10 v, 4 ma to 20 ma) 9.2.1 design requirements for this application, the design requirements are: ? 4-ma to 20-ma input with less than 20- ? burden ? 20-ma input with less than 20- ? burden ? 10-v input with impedance of approximately 100 k ? ? maximum 4-ma to 20-ma or 20 ma burden voltage equal to 0.4 v ? output range within 0 v to 5 v 9.2.2 detailed design procedure there are two modes of operation for the circuit shown in figure 69 : current input and voltage input. this design requires r 1 > > r 2 > > r 3 . given this relationship, equation 3 calculates the current input mode transfer function. where ? g represents the gain of the instrumentation amplifier ? v d represents the differential voltage at the ina821 inputs ? v ref is the voltage at the ina821 ref pin ? i in is the input current (3) equation 4 shows the transfer function for the voltage input mode. where ? v in is the input voltage (4) r 1 sets the input impedance of the voltage input mode. the minimum typical input impedance is 100 k . the r 1 value is 100 k because increasing the r 1 value increases noise. the value of r 3 must be small compared to r 1 and r 2 . the value of r 3 is 20 because that resistance value is smaller than r 1 and yields an input voltage of 400 mv when operating in current mode ( 20 ma). v = v g + v = g + v out v d ref - - ref v in r 2 r + r 1 2 r g = 10.4 n? r 3 = 20 ? r 2 = 4.17 n? r 1 = 100 n? ina821 v out 10 v 20 ma 2.5 v 2.3 v +vs -vs ref copyright ? 2017, texas instruments incorporated 15 v ref5025 1 f v out nr v in gnd 1 f 1 f 15 v -15 v -in +in rg rg out v = v g + v = (i r ) g + v out i d ref in 3 - - ref
32 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) use equation 5 to calculate r 2 if v d = 400 mv, v in = 10 v, and r 1 = 100 k . (5) the value from equation 5 is not a standard 0.1% value, so 4.17 k is selected. r 1 and r 2 use 0.1% tolerance resistors to minimize error. use equation 6 to calculate the gain of the instrumentation amplifier. (6) equation 7 calculates the gain-setting resistor value using the ina821 gain equation ( equation 1 .) (7) use a standard 0.1% resistor value of 10.5 k for this design. 9.2.3 application curves figure 70 and figure 71 show typical characteristic curves for the circuit in figure 69 . figure 70. plc output voltage vs input voltage figure 71. plc output voltage vs input current : : : g 49.4 k 49.4 k r 10.4 k g 1 5.75 1 r v 1 d v v in - d r 2 r + r 1 2 v = v r d in 2 = ? = 4.167 k w v v out ref - v d g = = = 5.75 4.8 v 2.5 v 400 mv - vv 0 1 2 3 4 5 -20 -10 0 10 20 output voltage (v) input current (ma) c001 0 1 2 3 4 5 -10 -5 0 5 10 output voltage (v) input voltage (v) c001
33 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.3 other application examples 9.3.1 resistance temperature detector interface figure 72 illustrates a 3-wire interface circuit for resistance temperature detectors (rtds). the circuit incorporates analog linearization and has an output voltage range from 0 to 5 v. the linearization technique employed is described in analog linearization of resistance temperature detectors . series and parallel combinations of standard 1% resistor values are used to achieve less than 0.02 c of error over a 200 c temperature span. figure 72. a 3-wire interface for rtds with analog linearization figure 73. transfer function of 3-wire rtd interface figure 74. temperature error over full temperature range 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 50 100 150 200 output voltage (v) temperature ( ? c) c001 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0 50 100 150 200 error ( ? c) temperature ( ? c) c001 -in +in ref +vs -vs ina821 15 v v out 0 v at 0c 5 v at 200c 25 mv/c -15 v copyright ? 2017, texas instruments incorporated 4.99 k 4.99 k 100 pt100 rtd 100 105 k 801 1.18 k ref5050 100 k 1 f v out nr v in gnd 1 f 1 f out rg rg
34 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations the nominal performance of the ina821 is specified with a supply voltage of 15 v and midsupply reference voltage. the device operates using power supplies from 2.25 v (4.5 v) to 18 v (36 v) and non midsupply reference voltages with excellent performance. parameters that can vary significantly with operating voltage and reference voltage are shown in typical characteristics . 11 layout 11.1 layout guidelines attention to good layout practices is always recommended. for best operational performance of the device, use good pcb layout practices, including: ? take care to ensure that both input paths are well-matched for source impedance and capacitance to avoid converting common-mode signals into differential signals. even slight mismatch in parasitic capacitance at the gain setting pins can degrade cmrr over frequency. for example, in applications that implement gain switching using switches or photomos ? relays to change the value of r g , select the component so that the switch capacitance is as small as possible and most importantly so that capacitance mismatch between the rg pins is minimized. ? noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device. bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. ? connect low-esr, 0.1- f ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. a single bypass capacitor from v+ to ground is applicable for single- supply applications. ? to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. if these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in parallel with the noisy trace. ? place the external components as close to the device as possible. as shown in figure 75 , keep r g close to the pins to minimize parasitic capacitance. ? keep the traces as short as possible.
35 ina821 www.ti.com sbos893a ? august 2018 ? revised december 2018 product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 75. example schematic and associated pcb layout out r3 +in -in +v out -v r1 r2 c1 c2 rg ref +vs vs ina821 rg in 8 +vs rg 7 out rg 6 ref 4 +in 5 -vs 1 2 3 r2 gnd +in r3 in use ground pours for shielding the input signal pairs r1 gnd +v c2 -v c1 low-impedance connection for reference terminal place bypass capacitors as close to ic as possible ref copyright ? 2017, texas instruments incorporated
36 ina821 sbos893a ? august 2018 ? revised december 2018 www.ti.com product folder links: ina821 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? ref50xx low-noise, very low drift, precision voltage reference ? opa191 low-power, precision, 36-v, e-trim cmos amplifier ? tina-ti software folder ? ina common-mode range calculator 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. bluetooth is a registered trademark of bluetooth sig, inc. photomos is a registered trademark of panasonic electric works europe ag. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 21-dec-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ina821id preview soic d 8 75 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 ina821 INA821IDR preview soic d 8 2500 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 ina821 pina821id active soic d 8 75 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 21-dec-2018 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

important notice and disclaimer ti provides technical and reliability data (including datasheets), design resources (including reference designs), application or other design advice, web tools, safety information, and other resources ? as is ? and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third party intellectual property rights. these resources are intended for skilled developers designing with ti products. you are solely responsible for (1) selecting the appropriate ti products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. these resources are subject to change without notice. ti grants you permission to use these resources only for development of an application that uses the ti products described in the resource. other reproduction and display of these resources is prohibited. no license is granted to any other ti intellectual property right or to any third party intellectual property right. ti disclaims responsibility for, and you will fully indemnify ti and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. ti ? s products are provided subject to ti ? s terms of sale ( www.ti.com/legal/termsofsale.html ) or other applicable terms available either on ti.com or provided in conjunction with such ti products. ti ? s provision of these resources does not expand or otherwise alter ti ? s applicable warranties or warranty disclaimers for ti products. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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